Solo Engineer Spent Seven Years Building A Handheld's Custom Chip
The RISCBoy core, an RV32IMC RISC-V design running on an iCE40 FPGA, has logged 736 commits since 2018 without a finished PCB.
- The RV32IMC CPU passes official RISC-V compliance and formal verification suites, per the repo.
- Design targets the iCE40-HX8k FPGA, with experimental support added for the Lattice ECP5.
- Repository shows 736 commits and 313 stars, mostly C and Verilog code, one author.
Why it matters: No lab, no company, no committee: one name owns every line of this chip's silicon.
RISCBoy GitHub repository (Wren6991) ↗ · ۲۰ تیر ۱۴۰۵۰۵/۴/۲۰ · ✓ Checked✓